Advanced VLSI & RTL Design
Hands-on RTL design and verification program with real projects and mentors from industry.
Who should attend
Engineers, fresh graduates and professionals seeking roles in RTL/verification and physical design.
What you’ll learn
- SystemVerilog/Verilog RTL coding patterns
- Synthesis & timing basics
- Verification flow & testbench design
Duration & mode
12 weeks — Live online with recorded sessions and lab files.